Built In Test for VLSI: Pseudorandom Techniques

Digital Testing and the Need for Testable Design.

Principles of Testable Design.

Pseudorandom Sequence Generators.

Test Response Compression Techniques.

Shift-Register Polynomial Division.

Special-Purpose Shift-Register Circuits.

Random Pattern Built-In Test.

Built-In Test Structures.

Limitations and Other Concerns of Random Pattern Testing.

Test System Requirements for Built-In Test.

Appendix.

References.

Index.