Design of High-Performance Microprocessor CircuitsISBN: 978-0-7803-6001-3
Hardcover
584 pages
October 2000, Wiley-IEEE Press
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Preface.
OVERVIEW.
Impact of Physical Technology on Architecture (John H. Edmondson).
TECHNOLOGY ISSUES.
CMOS Scaling and Issues in SUB-0.25µm Systems (Yuan Taur).
Techniques for Leakage Power Reduction (Vivek De, Yibin Ye, et al.).
Low-Voltage Technologies (Tadahiro Kuroda and Takayasu Sakurai).
SOI Technology and Circuits (Ghavam G. Shahidi, Fari Assaderaghi and Dimitri Antoniadis).
Models of Process Variations in Device and Interconnect (Duane Boning and Sani Nassif).
CIRCUIT STYLES FOR LOGIC.
Basic Logic Families (Kerry Bernstein).
Issues in Dynamic Logic Design (Paul Gronowski).
Self-Timed Pipelines (Ted Williams).
High-Speed VLSI Arithmetic Units: Adders and Multipliers (Vojin G. Oklobdzija).
CLOCKING.
Clocked Storage Elements (Hamid Partovi).
Design of High-Speed CMOS PLLs and DLLs (John George Maneatis).
Clock Distribution (Daniel W. Bailey).
MEMORY SYSTEM DESIGN.
Register Files and Caches (Ronald Preston).
Embedded DRAM (Tadaaki Yamauchi and Michihiro Yamada).
INTERCONNECT AND I/O.
Analyzing On-Chip Interconnect Effects (Noel Menezes and Lawrence Pileggi).
Techniques for Driving Interconnect (Shannon V. Morton).
I/O and ESD Circuit Design (Stephen C. Thierauf and Warren R. Anderson).
High-Speed Electrical Signaling (Stefanos Sidropoulos, Chih-Kong Ken Yang, and Mark Horowitz).
RELIABILITY.
Electromigration Reliability (J. Joseph Clement).
Hot Carrier Reliability (Kaizad Mistry).
CAD TOOLS AND TEST.
Overview of Computer-Aided Design Tools (Yao-Tsung Yen).
Timing Verification (Victor Peng).
Design and Analysis of Power Distribution Networks (David Blaauw, Rajendran Panda, and Rajat Chaudhry).
Testing of High-Performance Processors (Dilip K. Bhavsar).
Index.
OVERVIEW.
Impact of Physical Technology on Architecture (John H. Edmondson).
TECHNOLOGY ISSUES.
CMOS Scaling and Issues in SUB-0.25µm Systems (Yuan Taur).
Techniques for Leakage Power Reduction (Vivek De, Yibin Ye, et al.).
Low-Voltage Technologies (Tadahiro Kuroda and Takayasu Sakurai).
SOI Technology and Circuits (Ghavam G. Shahidi, Fari Assaderaghi and Dimitri Antoniadis).
Models of Process Variations in Device and Interconnect (Duane Boning and Sani Nassif).
CIRCUIT STYLES FOR LOGIC.
Basic Logic Families (Kerry Bernstein).
Issues in Dynamic Logic Design (Paul Gronowski).
Self-Timed Pipelines (Ted Williams).
High-Speed VLSI Arithmetic Units: Adders and Multipliers (Vojin G. Oklobdzija).
CLOCKING.
Clocked Storage Elements (Hamid Partovi).
Design of High-Speed CMOS PLLs and DLLs (John George Maneatis).
Clock Distribution (Daniel W. Bailey).
MEMORY SYSTEM DESIGN.
Register Files and Caches (Ronald Preston).
Embedded DRAM (Tadaaki Yamauchi and Michihiro Yamada).
INTERCONNECT AND I/O.
Analyzing On-Chip Interconnect Effects (Noel Menezes and Lawrence Pileggi).
Techniques for Driving Interconnect (Shannon V. Morton).
I/O and ESD Circuit Design (Stephen C. Thierauf and Warren R. Anderson).
High-Speed Electrical Signaling (Stefanos Sidropoulos, Chih-Kong Ken Yang, and Mark Horowitz).
RELIABILITY.
Electromigration Reliability (J. Joseph Clement).
Hot Carrier Reliability (Kaizad Mistry).
CAD TOOLS AND TEST.
Overview of Computer-Aided Design Tools (Yao-Tsung Yen).
Timing Verification (Victor Peng).
Design and Analysis of Power Distribution Networks (David Blaauw, Rajendran Panda, and Rajat Chaudhry).
Testing of High-Performance Processors (Dilip K. Bhavsar).
Index.
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