Monolithic Phase-Locked Loops and Clock Recovery Circuits: Theory and Design

Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits—A Tutorial (B. Razavi).

BASIC THEORY.

Theory of AFC Synchronization (W. Gruen).

Color-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television (D. Richman).

Charge-Pump Phase-Locked Loops (F. Gardner).

z-Domain Model for Discrete-Time PLLs (J. Hein & J. Scott).

Analyze PLLs with Discrete Time Modeling (J. Kovacs).

Properties of Frequency Difference Detectors (F. Gardner).

Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery (D. Messerschmitt).

Analysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission (E. Roza).

Optimization of Phase-Locked Loop Performance in Data Recovery Systems (R. Co & J. Mulligan).

Noise Properties of PLL Systems (V. Kroupa).

PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design (B. Kim, et al.).

Practical Approach Augurs PLL Noise in RF Synthesizers (M. O'Leary).

The Effects of Noise in Oscillators (E. Hafner).

A Simple Model of Feedback Oscillator Noise Spectrum (D. Leeson).

Noise in Relaxation Oscillators (A. Abidi & R. Meyer).

Analysis of Timing Jitter in CMOS Ring Oscillators (T. Weigandt, et al.).

Analysis, Modeling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators (B. Razavi).

BUILDING BLOCKS.

Start-up and Frequency Stability in High-Frequency Oscillators (N. Nguyen & R. Meyer).

MOS Oscillators with Multi-Decade Tuning Range and Gigahertz Maximum Speed (M. Banu).

A Bipolar 1 GHz Multi-Decade Monolithic Variable-Frequency Oscillator (J. Wu).

A Digital Phase and Frequency Sensitive Detector (J. Brown).

A 3-State Phase Detector Can Improve Your Next PLL Design (C. Sharpe).

GaAs Monolithic Phase/Frequency Discriminator (I. Shahriary, et al.).

A New Phase-Locked Loop Timing Recovery Method for Digital Regenerators (J. Bellisio).

A Phase-Locked Loop with Digital Frequency Comparator for Timing Signal Recovery (J. Afonso, et al.).

Clock Recovery from Random Binary Signals (J. Alexander).

A Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb/s (A. Pottbacker, et al.).

A Self-Correcting Clock Recovery Circuit (C. Hogge).

MODELING AND SIMULATION.

An Integrated PLL Clock Generator for 275 MHz Graphic Displays (G. Gutierrez & D. DeSimone).

The Macro Modeling of Phase-Locked Loopes for the SPICE Simulator (M. Sitkowski).

Modeling and Simulation of an Analog Charge Pump Phase-Locked Loop (S. Can & Y. Sahinkaya).

Mixed-Mode Simulation of Phase-Locked Loops (B. Antao, et al.).

Behavioral Representation for VCO and Detectors in Phase-Lock Systems (E. Liu & A. Sangiovanni-Vincentelli).

Behavioral Simulation Techniques for Phase/Delay-Locked Systems (A. Demir, et al.).

PHASE-LOCKED LOOPS.

A Monolithic Phase-Locked Loop with Detection Processor (E. Murthi).

A 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors (K. Ware, et al.).

High-Frequency Phase-Locked Loops in Monolithic Bipolar Technology (M. Soyuer & R. Meyer).

A 6-GHz Integrated Phase-Locked Loop Using AlGaAs/GaAs Heterojunction Bipolar Transistors (A. Buchwald, et al.).

A 6-GHz 60-mW BiCMOS Phase-Locked Loop with 2-V Supply (B. Razavi & J. Sung).

Design of PLL-Based Clock Generation Circuits (D. Jeong).

A Variable Delay Line PLL for CPU-Coprocessor Synchronization (M. Johnson & E. Hudson).

A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors (I. Young, et al.).

A Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors (J. Alvarez, et al.).

A 30-128 MHz Frequency Synthesizer Standard Cell (R. Bitting & W. Repasky).

Cell-Based Fully Integrated CMOS Frequency Synthesizers (D. Mijuskovic, et al.).

Fully-Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ±50 psec Jitter (I. Novof, et al.).

PLL Design for a 500 MB/s Interface (M. Horowitz, et al.).

CLOCK AND DATA RECOVERY CIRCUITS.

An Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance (S. Sun).

A 30-MHz Hybrid Analog/Digital Clock Recovery Circuit in 2-μm CMOS (B. Kim, et al.).

A BiCMOS PLL-Based Data Separator Circuit with High Stability and Accuracy (S. Miyazawa, et al.).

A Versatile Clock Recovery Architecture and Monlithic Implementation (L. De Vito).

A 155-MHz Clock Recovery Delay- and Phase-Locked Loop (T. Lee & J. Bulzacchelli).

A Monolithic 156 Mb/s Clock and Data Recovery PLL Circuit using the Sample- and-Hold Technique (N. Ishihara & Y. Akazawa).

A Monolithic 480 Mb/s Parallel AGC/Decision/Clock Recovery Circuit in 1.2-μm CMOS (T. Hu & P. Gray).

A Monolithic 622 Mb/sec Clock Extraction and Data Retiming Circuit (B. Lai & R. Walker).

A 660 Mb/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission (M. Banu & A. Dunlop).

A Monolithic 2.3-Gb/s 100-mW Clock and Data Recovery Circuit in Silicon Bipolar Technology (M. Soyuer).

A 50 MHz Phase- and Frequency-Locked Loop (R. Cordell, et al.).

NMOS ICs for Clock and Data Regeneration in Gigabit-per-Second Optical-Fiber Receivers (S. Enam & A. Abidi).

A PLL-Based 2.5-Gb/s Clock and Data Regenerator IC (H. Ransijn & P. O'Connor).

A 2.5-Gb/sec 15-mW BiCMOS Clock Recovery Circuit (B. Razavi & J. Sung).

An 8 GHz Silicon Bipolar Clock Recovery and Data Regenerator IC (A. Pottbacker & U. Langmann).

Author Index.

Subject Index.

Editor's Biography.