Verilog Coding for Logic SynthesisISBN: 978-0-471-42976-0
Hardcover
309 pages
April 2003
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Table of Figures.
Table of Examples.
List of Tables.
Preface.
Acknowledgments.
Trademarks.
Introduction.
Asic Design Flow.
Verilog Coding.
Coding Style: Best-Known Method for Synthesis.
Design Example of Programmable Timer.
Design Example of Programmable Logic Block for Peripheral Interface.