Signal Integrity Effects in Custom IC and ASIC Designs

"In the era of System-on-Chip, when large portions of the overall system are integrated on one large chip, designers are facing increasingly challenging issues. For the first time, this book is taking a closer look at the signal integrity problems faced by both high-performance and cost-performance applications, digital and mixed-signal integrated circuits. System designers are given guidance in power distribution analysis, interconnect optimization, and mixed, digital-analog circuit integration challenges. Researchers and CAD engineers can get an in-depth view of the current and future requirements for full-chip CAD tools, on-chip transmission line designs, integrated passive components, and many other critical signal integrity issues. This book is bringing together a broad range of representative papers that will further the understanding both in the industrial and academic communities."
(Alina Deutsch, Research Staff Member, T.J. Watson Research Center, International Business Machines)

"Electrical integrity (or environment noise) is becoming the principal obstacle in system-on-a-chip design. Digital circuits create a very noisy environment in which other digital and analog circuits must function. This environmental noise comes about because of coupling through the interconnect, power supply, and substrate. This book surveys the latest literature on electrical integrity analysis and design and is, therefore, an invaluable resource for anyone designing systems-on-a-chip."
(Kenneth L. Shepard, Professor, Columbia University)

"The explosion of wireless communications that offer greater mobility and broadband communications that provide super fast access to the Internet have placed new demands on IC designers. The key to developing successful Systems on Chip designs that offer Analog and Mixed Signal capabilities is the approach used to extract and analyze the affects of parasitics on signal integrity. This book offers a tutorial guide to IC designers who want to move to the next level of chip design by unlocking the secrets of signal integrity."
(Jake Buurma Senior Vice President, Worldwide Research & Development, Cadence Design Systems, Inc.)

"As technology scales to .1 micron and below, second order effects due to physical phenomena that were not much visible before start playing a more and more significant role. So much so that well-established methodologies and tools are not providing the necessary level of confidence to the designer that her/his integrated circuit will perform as planned. The need for more accurate extraction and analysis is obvious when we observe horror stories about very hard to detect intermittent faults created by interactions among signals on different wires. There are two complementary approaches to the problem that come to mind as always when we go over the limit of previous methods - increase the accuracy of the analysis tools, and/or solve the problems by imposing constraints on the degrees of freedom left to the designer. This collection of papers covers both in details. It is the most comprehensive syllabus of important results for researchers and designers on the topic. I highly recommend to read it and to pay attention to the messages given by the papers of the collection."
(Alberto Sangiovanni-Vincentelli, Professor, University of California Berkeley)