Advanced Frequency Synthesis by Phase Lock

Preface xv

Symbols List and Glossary xix

1 Introduction 1

1.1 Phase-Locked Synthesizer 2

1.2 Fractional-N Frequency Synthesis 3

1.3 Representing a Change in Divide Number 3

1.4 Units 5

1.5 Representing Phase Noise 5

1.6 Phase Noise at the Synthesizer Output 7

1.7 Observing the Output Spectrum 7

2 Fractional-N and Basic ΣΔ Synthesizers 9

2.1 First-Order Fractional-N 9

2.1.1 Canceling Quantization Noise 11

2.1.2 Cancellation with a PFD 13

2.1.3 Cancellation Techniques 15

2.1.4 Spectrum without Cancellation 16

2.1.5 Influence of N 17

2.2 Second-Order Fractional-N 17

2.2.1 Purpose 17

2.2.2 Form 18

2.2.3 Performance 19

2.2.4 Interpreting the Spectrum 21

2.3 Higher Order Fractional-N 24

2.3.1 Constant Sampling Rate 25

2.3.2 Noise Shaping Versus Cancellation 28

2.3.3 Effect of a Varying Sampling Rate 28

2.4 Spectrums with Constant Sampling Rate 31

2.4.1 100.625 MHz with Zero Initial Condition 31

2.4.2 100.62515... with Zero Initial Condition 34

2.4.3 100.625 MHz with Seed 36

2.5 Summary of Spectrums 36

2.6 Summary 36

3 Other Spurious Reduction Techniques 39

3.1 LSB Dither 39

3.2 Maximum Sequence Length 43

3.3 Shortened Accumulators and Lower Primes 48

3.4 Long Sequence 51

3.5 Summary 53

4 Defects in ΣΔ Synthesizers 55

4.1 Noise Models 55

4.1.1 VCO Noise 55

4.1.2 Basic-Reference Noise 56

4.1.3 Equivalent Input Noise 56

4.1.4 ΣΔ Quantization Noise 57

4.1.5 Parameter Dependence 57

4.1.6 Synthesizer Output Noise 57

4.1.6.1 Nominal Parameters 59

4.1.6.2 Higher F_out 60

4.1.6.3 Higher F_ref 62

4.1.6.4 Summary 63

4.2 Levels of Other Noise in ΣΔ Synthesizers 64

4.2.1 Dither 65

4.2.2 Varying Sample Rate 65

4.2.3 Mismatched (Unbalanced) Charge Pumps 66

4.2.4 Levels for All Four Loop Configurations 67

4.2.5 Simple Charge Pump 69

4.2.6 System Performance 71

4.3 Noise Sources, Equivalent Input Noise 71

4.3.1 Without ΣΔ Modulation 72

4.3.2 Increase with ΣΔ Modulation 73

4.4 Discrete Sidebands 74

4.4.1 At Offsets Related to f_fract 74

4.4.1.1 Due to Current Mismatch 74

4.4.1.2 Not Necessarily Related to Mismatch 75

4.4.2 At Offsets of nF_ref 75

4.4.2.1 Due to SD Modulation 76

4.4.2.2 Due to Delays in the PFD 77

4.4.2.3 Due to Leakage Current 77

4.4.2.4 Due to All Three 77

4.4.2.5 With Resampling 78

4.4.2.6 Significance of Levels 78

4.4.3 Charge Pump Dead Zone 80

4.5 Summary 80

5 Other ΣΔ Architectures 81

5.1 Stability 81

5.2 Feedback 82

5.3 Feedforward 85

5.4 Quantizer Offset 89

5.5 MASH-n₁n₂n₃ 91

5.6 Cancellation of Quantization Noise in the General Modulator 92

5.7 Fractional Swallows 93

5.7.1 Resulting Spurs 96

5.7.2 Estimate of Achievable Suppression 96

5.7.3 Fractional Swallows in a ΣΔ Synthesizer 96

5.8 Hardware Reduction 97

5.8.1 Analysis 97

5.8.2 Simulation 100

6 Simulation 103

6.1 SandH.mdl 103

6.1.1 The Synthesizer Loop 105

6.1.2 MASH Modulator 105

6.1.3 Setting Parameters 105

6.1.4 Accumulator Size 106

6.1.5 Scopes 107

6.1.6 Spectrum Analyzers 107

6.1.7 Spectrums Observed 108

6.1.8 Reason for Frequency Conversion 110

6.1.9 Synchronization 111

6.2 SandHreverse.mdl 111

6.3 CPandI.mdl 111

6.4 Dither.mdl 111

6.5 HandK.mdl 113

6.6 SimplePD.mdl 114

6.7 CPandIplus.mdl 114

6.7.1 CP Balance 114

6.7.2 PFD Delays 116

6.7.3 Data Acquisition 116

6.7.4 Log Plots 116

6.8 CPandITrunc.mdl 117

6.9 Adapting a Model 118

6.10 EFeedback.mdl 118

6.11 FeedForward.mdl 120

6.12 MASH modulator scripts 120

6.13 SynStep__.mdl 121

6.14 Other Methods 121

7 Diophantine Synthesizer 123

7.1 Two-Loop Synthesizer 124

7.2 Multi Loop Synthesizers 126

7.3 MATLAB Scripts 126

7.3.1 loop2tune 126

7.3.2 loopxtune 128

7.3.3 Algorithm 128

7.4 Signal Mixing 129

7.5 Reference-Frequency Coupling 132

7.6 Center Frequencies 133

8 Operation at Extreme Bandwidths 135

8.1 Determining the Effects of Sampling 135

8.2 A Particular Case 136

8.3 When are Sampling Effects Important? 141

8.4 Computer Program 141

8.5 Sampling Effects in ΣΔ Synthesizers 141

9 All-Digital Frequency Synthesizers 145

9.1 The Flying Adder Synthesizer 146

9.1.1 The Concept 146

9.1.2 Frequencies Generated 147

9.1.3 Jitter 149

9.1.4 Suppression of Spurs 150

9.1.5 Further Development 151

9.2 ADPLL Synthesizer 151

9.2.1 ADPLL Concept 151

9.2.2 The Numbers 152

9.2.3 Mathematical Representation 152

9.2.4 DCO 153

9.2.5 Loop Filter 154

9.2.6 Synchronization 154

9.2.7 Phase Noise 154

9.2.7.1 In-Band Noise, Critical Source 154

9.2.7.2 Improving Resolution 155

9.2.8 Reference Spurs 157

9.2.9 Fractional Spurs 157

9.2.10 Modulation Response 159

9.2.11 ΣΔ Cancellation 159

9.2.12 Simulation 159

9.2.13 Dead Zone 160

Appendix A. All Digital 163

A.1 Flying Adder Circuits 163

A.2 ADPLL Synthesizer 164

A.2.1 Alternative Architecture 164

A.2.2 Reference Jitter and the Dead Zone 165

A.2.3 Reference Jitter and Calibration 167

A.2.4 Initial Plan for a Model of an ADPLL Synthesizer 168

Appendix C. Fractional Cancellation 171

C.1 Modulator Details 171

C.2 First Accumulator 173

C.3 Second Accumulator 173

C.4 Additional Accumulators 174

C.5 Accumulator without Input Register 176

Appendix E. Excess PPSD 177

E.1 Development of Eq. (2.4) 177

E.2 Approximating k_p as constant 180

E.3 Approximation in Eq. (E.8) 181

Appendix F. References to FS2 183

Appendix G. Using GSMPL 185

G.1 Open-Loop Transfer Function 185

G.1.1 Without Sampling 185

G.1.2 Using Gsmpl 186

G.1.3 Sampling Effects 186

G.2 Closed-Loop Responses 187

G.3 Saving Results 187

G.4 Version Number 187

G.5 Example Session 187

G.6 Generating Analysis Plots 189

G.7 Verification of Gardner’s Stability Limits 191

G.8 The Nyquist Plot 192

G.8.1 Without Sampling 193

G.8.2 With Sampling 193

Appendix H. Sample-and-Hold Circuit 195

H.1 Transient Performance 195

H.1.1 No Sampling 196

H.1.2 Ideal Sampler 196

H.1.3 Hold with Integrator 196

H.1.4 Modified Hold with Integrator 200

H.2 Filter Capacitor Before Sampler 202

Appendix L. Loop Response 207

L.1 Primary Loop 207

L.1.1 Open-Loop Transfer Function 207

L.1.2 Error Transfer Function 208

L.1.3 Forward Transfer Function 209

L.1.4 Output PPSD Shape 211

L.2 Damped Loop 213

Appendix M. Mash PSD 215

M.1 MASH Modulator: First Stage 217

M.2 MASH Modulator: Second Order 219

M.3 MASH Modulator: Higher Order 219

M.4 Variances 221

M.5 Some Parameters of S 222

M.6 Previous Development 222

M.7 Some MASH Modulator Characteristics 222

M.8 Characteristics of MATLAB scripts mashone and mashall_ 223

Appendix N. Sampled Noise 225

N.1 Case 1: W_n ≪ f_ref 225

N.2 Case 2: 1/ T ≫ Wn ≫ f_ref 225

N.3 Case 3: W_n ≫ 1/ T ≫ f_ref 226

N.4 Variance of Sampled Noise (1/ T ≫ f_ref) 226

N.5 Convolution of PSDs 227

N.6 Representing Squared PSDs 228

Appendix O. Oscillator Spectrums 229

Appendix P. Phase Detectors 231

Appendix Q. Quantization PPSD 233

Q.1 Development of Eq. (Q.1) 234

Q.2 Superposition 235

Q.3 New Synthesized Frequency 236

Q.4 Loop Response 237

Q.5 Verification of the Effect of Sampling on the Loop 237

Appendix R. Reference Frequency Spurs 241

R.1 Leakage Current 242

R.2 Pulse Offset 242

R.3 ΣΔ Modulation 243

R.4 Effect of ΣΔ Modulation on Pulse Offset Spurs 244

R.5 Effect of ΣΔ Modulation on Leakage Spurs 247

R.6 Effects of Resampling 247

Appendix S. Spectrum Analysis 249

S.1 Spectrums 249

S.1.1 Periodicity 249

S.1.2 Accurate Representation 250

S.1.3 Approximate Representation 251

S.1.4 Representation of a Sequence 252

S.2 The Spectrum Analyzer 253

S.3 The Window Function 253

S.4 Density and Discrete Spurs 254

S.5 Control Parameters 255

S.6 Frequency Conversion in an Analyzer 255

S.7 Displaying L, FPSD, and PPSD 256

S.8 Spectral Overlaps 256

S.8.1 Aliasing 256

S.8.2 Spectral Folding 257

S.8.3 Image 258

S.9 Anomalous Spurs 258

Appendix T. Toolboxes 259

Appendix U. Noise Produced By Charge Pump Current Unbalance (Mismatch) 261

Appendix W. Getting Files From the Wiley Internet Site 265

Appendix X. Some Tables 267

X.1 Accumulator Shortening 267

X.2 Sequence Lengths 268

End Notes 269

References 277

Index 283