RF Circuit Design

PART I INDIVIDUAL RF BLOCKS.

1. LNA (LOW NOISE AMPLIFIER).

1.1 Introduction.

1.2 Single-Ended Single Device LNA.

1.3 Single-Ended Cascode LNA.

1.4 LNA with AGC (Automatic Gain Control).

2. MIXERS.

2.1 Introduction.

2.2 Passive Mixers.

2.3 Active Mixers.

2.4 Design Schemes.

3. DIFFERENTIAL PAIRS.

3.1 Why Differential Pairs?

3.2 Can DC Offset be Blocked by a Capacitor?

3.3 Fundamentals of Differential Pairs.

3.4 CMRR (Common Mode Rejection Ratio).

4. RF BALUN.

4.1 Introduction.

4.2 Transformer Baluns.

4.3 LC Baluns.

4.4 Micro Strip Line Baluns.

4.5 Mixed Types of Baluns.

5. TUNABLE FILTERS.

5.1 Tunable Filters in Communication Systems.

5.2 Coupling Between Two Tank Circuits.

5.3 Circuit Description.

5.4 Effect of Second Coupling.

5.5 Performance.

6. VCO (VOLTAGE-CONTROLLED OSCILLATOR)

6.1 “Three-Point” Type Oscillators.

6.2 Other Single-Ended Oscillators.

6.3 VCO and PLL.

6.4 Design Example of a Single-Ended VCO.

6.5 Differential VCO and Quad Phases VCO.

7. POWER AMPLIFIERS (PA).

7.1 Classifications of Power Amplifiers.

7.2 Single-Ended PA Design.

7.3 Single-Ended PA-IC Design.

7.4 Push-Pull PA Design.

7.5 PA with Temperature Compensation.

7.6 PA with Output Power Control.

7.7 Linear PA.

PART II DESIGN TECHNOLOGIES AND SCHEMES.

8. DIFFERENT METHODOLOGY BETWEEN RF AND DIGITAL CIRCUIT DESIGN.

8.1 Controversy.

8.2 Differences between RF and Digital Blocks in a Communication System.

8.3 Conclusion.

8.4 Notes for High-Speed Digital Circuit Design.

9. VOLTAGE AND POWER TRANSPORTATION.

9.1 Voltage Delivered from a Source to a Load.

9.2 Power Delivered from a Source to a Load.

9.3 Impedance Conjugate Matching.

9.4 Additional Effects of Impedance Matching.

10. IMPEDANCE MATCHING IN NARROW-BAND CASE.

10.1 Introduction.

10.2 Impedance Matching by Means of Return Loss Adjustment.

10.3 Impedance Matching Network Built of One Part.

10.4 Impedance Matching Network Built of Two Parts.

10.5 Impedance Matching Network Built of Three Parts.

10.6 Impedance Matching When ZS or ZL Is Not 50 Ω.

10.7 Parts in an Impedance Matching Network.

11. IMPEDANCE MATCHING IN A WIDE-BAND CASE.

11.1 Appearance of Narrow- and Wide-Band Return Loss on a Smith Chart.

11.2 Impedance Variation Due to Insertion of One Part per Arm or per Branch.

11.3 Impedance Variation Due to the Insertion of Two Parts per Arm or per Branch.

11.4 Impedance Matching in IQ Modulator Design for a UWB System.

11.5 Discussion of Wide-band Impedance Matching Networks.

12. IMPEDANCE AND GAIN OF A RAW DEVICE.

12.1 Introduction.

12.2 Miller Effect.

12.3 Small Signal Model of a Bipolar Transistor.

12.4 Bipolar Transistor with CE (Common Emitter) Configuration.

12.5 Bipolar Transistor with CB (Common Base) Configuration.

12.6 Bipolar Transistor with CC (Common Collector) Configuration..

12.7 Small Signal Model of a MOSFET Transistor

12.8 Similarity between Bipolar and MOSFET Transistors.

12.9 MOSFET Transistor with CS (Common Source) Configuration.

12.10 MOSFET Transistor with CG (Common Gate) Configuration.

12.11 MOSFET Transistor with CD (Common Drain) Configuration.

12.12 Comparison of Bipolar and MOSFET Transistors in Various Configurations.

13. IMPEDANCE MEASUREMENT.

13.1 Introduction.

13.2 Scale and Vector Voltage Measurement.

13.3 Direct Impedance Measurement by Network Analyzer.

13.4 Alternative Impedance Measurement by Network Analyzer.

13.5 Impedance Measurement with the Assistance of a Circulator.

Appendices.

References.

14. GROUNDING.

14.1 Implications of Grounding.

14.2 Possible Grounding Problems Hidden in a Schematic.

14.3 Imperfect or Inappropriate Grounding Examples.

14.4 “Zero” Capacitor.

14.5 Quarter Wavelength of Micro Strip Line.

15. EQUIPOTENTIALITY AND CURRENT COUPLING ON THE GROUND SURFACE.

15.1 Equipotentiality on the Ground Surface.

15.2 Forward and Return Current Coupling.

15.3 PCB or IC Chip with Multi-metallic Layers.

16. RFIC (RADIO FREQUENCY INTEGRATED CIRCUIT) AND SOC  (SYSTEM ON CHIP).

16.1 Interference and Isolation.

16.2 Shielding for an RF Module by a Metallic Shielding Box.

16.3 Strong Desirability to Develop RFIC.

16.4 Interference Going Along an IC Substrate Path.

16.5 Solution for Interference Coming from the Sky.

16.6 Common Grounding Rules for an RF Module and RFIC Design.

16.7 Bottlenecks in RFIC Design.

16.8 Prospect of SOC.

16.9 What Is Next?

17. MANUFACTURABILITY OF PRODUCT DESIGN.

17.1 Introduction.

17.2 Implication of 6σ Design.

17.3 Approaching 6σ Design.

17.4 Monte Carlo Analysis.

PART III RF SYSTEM ANALYSIS.

18. MAIN PARAMETERS AND SYSTEM ANALYSIS IN RF CIRCUIT DESIGN.

18.1 Introduction.

18.2 Power Gain.

18.3 Noise.

18.4 Non-Linearity.

18.5 Other Parameters.

18.6 Example of RF System Analysis.

Appendices.

References.

INDEX.