FSM-based Digital Design using Verilog HDL

Peter D. Minns, Northumbria University, School of Computing, Engineering, and Information Sciences, Newcastle Upon Tyne
Dr Peter Minns has been at Northumbria University since 1984, now holding the position of Senior Lecturer in the School of Computing, Engineering and Information Sciences. He teaches courses on electrical circuit theory, electronics, programming and embedded system design to both undergraduates and post graduates, and is also involved in teaching company schemes in industry. Previous to this, he has worked for many years as a practising engineer specializing in both the telecommunications and embedded microprocessor fields. His current research interest is in the development of finite state machines (FSMs).

Ian David Elliott, Northumbria University, School of Computing, Engineering, and Information Sciences, Newcastle Upon Tyne
Ian Elliott has been a lecturer in further and higher education for over 20 years, currently holding the position of Senior Lecturer in the School of Computing, Engineering and Information Sciences, at Northumbria University. He has taught a wide range of subjects in the field of electronics, as well as working as a consultant in industry, carrying out research into integrated circuit testing. He now specializes in hardware description languages, specifically Verilog-HDL and Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL). He was one of the first academics to introduce the topic of hardware description languages into the curriculum.